About

I am an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Minnesota, Twin Cities. My research interest resides at the intersection of Computer Architecture, Hardware Design, and Machine Learning (ML), with a recent focus on hardware acceleration for emerging ML models, such as large language models (LLMs). The central approach revolves around co-design across the computing stack (applications, algorithms, integrated systems, architectures, circuits, and devices) to achieve high-performance, efficient, and robust ubiquitous AI-powered functionalities. Following is an example that represents my research flavors: A holistic co-designed solution from an efficient architecture (SmartExchange ISCA'20), to a chip (i-FlatCam VLSI'22), and to an integrated system (i-FlatCam VLSI'22, EyeCoD ISCA'22 (Selected as IEEE Micro Top Picks'23)) for enabling efficient eye-tracking functionality on VR/AR derives. 

I was a postdoctoral researcher at the EIC lab of Georgia Institute of Technology, after obtaining my Ph.D. degree from Rice University. Both my postdoctoral and Ph.D. studies are under the supervision of Prof. Yingyan Lin. Before joining Rice, I was a Ph.D. student in Prof. Yuan Xie's group for one year and worked on DNN accelerator security and NoC chiplet design. I received my MS and BS degrees from Fudan University, China. During my MS. study, I was advised by Prof. Zhiliang Hong and was working on a digital radio-frequency transmitter.